(a) Field of the Invention
This invention relates to field effect transistors.
(b) Description of the Prior Art
Field effect transistors are developed as a kind of active element for directly controlling, by the gate voltage, majority carriers flowing through the semi-conductor channel from source to drain. However, since the conventional field effect transistors do not have a large apparent transconductance gm and do have a saturation characteristic, the conventional field effect transistors are not suitable for use in low impedance load high power and high frequency range operations.
To make clear the difference in the features of transistors embodying this invention and those of conventional field effect transistors, the latter are first described. With reference to FIG. 1, a conventional field effect transistor comprises a semiconductor crystal 1 of one conductivity type (n-type or p-type), a source electrode 2 ohmically provided at one end of the semiconductor crystal 1, a drain electrode 3 ohmically provided at the other end of the semiconductor crystal 1, and gates 4 and 4a provided at opposite sides of the semiconductor crystal 1. A dc power supply V.sub.DD is connected across the source 2 and the drain 3 for passing a drain current I.sub.D, while a dc bias supply V.sub.GG is connected across the source 2 and the gates 4 and 4a for controlling the drain current I.sub.D.
In addition to the above mentioned field effect transistor of the junction type, field effect transistors of the MOS type have been developed but operate in accordance with the principle similar to the junction type field effect transistor. In field effect transistors of the junction type, majority carriers are controlled by a control voltage in contrast to a current controlled transistor such as bipolar transistors, so that the junction FET has advantages, such as a high input impedance, no storage effect, a small noise figure and a good transfer characteristic. Accordingly, the junction FET has a wide application including amplification of, for example, a voice signal.
Now, reference is made to FIG. 2. In the lower source-drain voltage range, the drain current I.sub.D linearly increases along a line determined by the resistivity and geometric shape of the semiconductor crystal 1 (e.g. silicon) in accordance with Ohm's law. However, the drain current I.sub.D saturates in case the drain voltage exceeds a certain level which is called the pinch-off voltage V.sub.P as described below, so that the conventional FET has a saturation characteristic similar to that of a vacuum tube pentode. In accordance with the conventional theory, this saturation phenomenon has been explained that the depletion layers grow enough to close the conduction path in the channel. However, this closure of the conduction path fails to adroitly explain the fact that the current still continues flowing even after the pinch-off point V.sub.P. In order to obtain a solution of this problem, the inventor made an extensive study and a number of experiments. As a result, the inventor found that the saturation phenomenon is caused mainly by the behavior of the series resistance of especially the portion leading from the source to the pinch-off point. More specifically, below the pinch-off voltage V.sub.P, the active series resistance of the current path from the source electrode 2 up to the pinch-off point remains substantially small and constant because this path is sufficiently broad. Whereas, above the pinch-off voltage V.sub.P, the current path becomes narrowed causing said series resistance to increase to such an extent that the voltage drop caused by the drain current through this series resistance acts strongly to further inflate the depletion layer, so that the width of the current path becomes further narrower. Accordingly, this active series resistance which is represented by R.sub.S abruptly becomes much larger. This increase of the series resistance R.sub.S, in turn, acts to suppress the increasing trend of the drain current which would otherwise follow the increase of the drain voltage. This phenomenon may be interpreted as the so-called negative feed-back action within the FET.
The relation of the pinch-off voltage V.sub.P with the ionized impurity density N, the unit electron charge q, the half channel width a, the dielectric constant e of the semiconductor 1 and the gate voltage V.sub.G applied is as shown by the following equation (1): ##EQU1##
On the other hand, said pinch-off voltage V.sub.P has the relation with the total series resistance R.sub.S at pinch-off time and the saturated drain current I.sub.DSS as shown by the following equation (2): EQU V.sub.P =R.sub.S .multidot.I.sub.DSS ( 2)
Since the apparent transconductance gm is defined by: ##EQU2## there has been derived the consideration that the apparent transconductance gm is substantially equal to 1/R.sub.S.
The saturation characteristic relies also on the geometric dimension of the field effect transistor. With reference to FIG. 3 showing a conventional FET made by the usual planar technique and having an n-type channel 8, a source 6 and a drain 7 are provided on the same plane, with the distance between the source 6 and the channel 8 and the distance between the drain 7 and the channel 8 being relatively long. Moreover, the conventional FET has a long channel length L of more than several tens of micrometers and a length to half width ratio L/a of several tens to one hundred. The drain current is on the order of 10 milli-amperes, and the apparent transconductance gm is less than 10 millimhos whereas the output power is about 100 milli-watts.
Accordingly, the conventional FET is not suitable for use in low impedance load, high power and high frequency range operations.
The above defects of the conventional FET are caused by the relatively large value of the serial sum of the resistances in the source, from the source to the channel, and in the channel, i.e. the series resistance R.sub.S. In such a known FET, the channel is narrow and long so that the active resistance of this channel itself greatly increases in a non-linear manner in accordance with the spreading of the depletion layers. Thus, the saturation characteristic is caused to develop and the apparent transconductance gm will not be able to have a large value.
Now, let us here make some analytic discussion of the FET by introducing the conception that the FET is comprised of a combination of a first portion which is a real FET having no series resistance R.sub.S but having a true transconductance Gm and a second portion which is a series resistance R.sub.S. Then, the aforesaid apparent transconductance gm is expressed by the following equation (4) by taking into consideration the negative feed-back action of this series resistance R.sub.S : EQU gm=Gm/(1+R.sub.S .multidot.Gm) (4)
As will be apparent from this equation, when R.sub.S is large to give R.sub.S .multidot.Gm&gt;&gt;1, the relation g.sub.m .perspectiveto.1/R.sub.S will take place and it may be said that the measured apparent transconductance is, in reality, the inverse of the series resistance R.sub.S. Accordingly, it is only when R.sub.S .multidot.Gm&lt;&lt;1 that the relation g.sub.m .perspectiveto.G.sub.m is obtained, and thus an approximate value of the true transconductance Gm can be measured. In other words, in the state that a current I.sub.D is caused to flow by the application of an external drain voltage V.sub.D, the voltage which is actually applied to the portion functioning as the real FET is not V.sub.D but only (V.sub.D -I.sub.D R.sub.S) in view of the series resistance R.sub.S.
In the prior art, various attempts have been made to improve the performance characteristics of FET's by, for example, reducing the channel length to decrease the gate capacitance for improving the build-up characteristic as well as the high frequency operation. Such reduction of the channel length appears as if it would work so as to decrease this series resistance. In reality, however, the series resistance which was reduced in amount corresponding to the reduced channel length still showed a continuous rise with an increase in the drain voltage. The more closely the drain voltage approaches the pinch-off voltage, the quicker rises the rate of increase of this series resistance. This fact the increase in the series resistance of the channel provides the condition R.sub.S .multidot.G.sub.m &gt;1 and causes a decrease in the apparent transconductance gm. At the same time, this increase in R.sub.S together with the fact that the drain current is flowing will bring about an I.sub.D R.sub.S drop and the voltage V.sub.D -I.sub.D R.sub.S will hardly increase as stated previously even when V.sub.D is increased. Thus, the current will never increase.
In short, it can hereby be recognized once again that the conventional FET having a saturation characteristic is not a real FET but that it is, in fact, a combination of a real FET with a series resistance which would cause an extremely large increase in its value in accordance with an increase of the drain voltage and the drain current.
As a result of the research undertaken by the inventor, it has been confirmed that the existence of the saturation characteristic can never be avoided so long as the increase of the series resistance R.sub.S is not suppressed. This knowledge has led to the conclusion that the series resistance R.sub.S should be less than 1/Gm throughout the entire range of drain voltage in the operative state of the transistor. To accomplish this condition, the inventor provides such an FET that no narrow, lengthy current path will be formed for any drain voltage applied. Under the above mentioned condition, where the product R.sub.S .multidot.Gm is less than one throughout the entire range of drain voltage in the operative state, the apparent transconductance gm is substantially equal to the true transconductance Gm. However, the conventional FET cannot satisfy the above condition so that the apparent transconductance gm of such an FET has a small value.